Modern integrated circuit systems are increasingly large and complex to satisfy insatiable demands of applications desired from every aspect of human life. Design of a large and complex system with increased time-to-market pressure, however, can pose new challenges in design paradigm and in taming of test cost and test development effort. Conventional design-for-test (DFT) methods and generation-based test development can offer a limited success in coping with new design paradigms and test challenges and in meeting aggressive time-to-market constraint.
Aim of a large scale system integration such as the 3D IC integration is to provide a system with increased functionality, superior performance, lower manufacturing cost and higher reliability. Persistent time-to-market pressure can influence a design paradigm that encourages a hierarchical or core-based design approach to mitigate design challenges and to tame design complexity. The scheme employs the 3D IC to indicate a large system for the purposed of discussion.
Modern 3D IC can be a mixed-signal device that contains both analog and digital components. While the testing of analog circuits can be typically managed by application specific functional tests or built-in self-test (BIST), the digital counterpart can be commonly tested by structural test methods. Generation of the structural test patterns is often automated but their development time and effort can depend on size and complexity of device under test (DUT). Management of test cost and test development in an aggressive time-to-market business environment can be a challenging task.
Test cost and test development effort can be important factors for successful commercialization of 3D IC devices due to increased test complexity with respect to size and heterogeneity of constituting components. Test cost can be measured by test time and test data volume. Test time of structural tests can be dominated by time to deliver test data to device under test (DUT). Reduction of test cost can be achieved by enabling test solutions that maximize utilization of delivered test data so that total size of test data delivered can be minimized for the testing of the DUT.
Test development cost, in terms of development time and effort, can be as important as test cost from the competitive time-to-market point of view. Test development cost can be adversely affected by the size and complexity of the DUT. The test complexity can require increased engineering effort for efficient utilization of the available tests. Capability of commercial EDA tools and their runtime, for example, can be limited by size of the DUT. Current EDA tools may not be able to process entire 3D IC designs for automatic test pattern generation (ATPG) and automatic design-for-testability (DFT) hardware insertion. Conventional test isolation methods can aid to partition system into a set of subsystems for the ATPG and test one partition at a time. They, however, unnecessarily isolate cores under test from their system environment that they interact with and can offer limited flexibility in achieving high test data utilization and at-speed test coverage of interface logic among interacting cores.
The desirable DFT methods for the 3D IC system can independently integrate implemented DFT of cores without isolation from their system environment and compose test patterns of corresponding cores to form test patterns of any level of design hierarchy without referring to their design netlists. Composition of test patterns can be far more advantages than generation of test patterns in terms of test development cost because composition of test patterns can be many orders of magnitude cheaper than generation in terms of computational effort.
Due to testability constraint measured by controllability and observability, structural tests can be primarily applied to the testing of digital circuits. The most commonly employed DFT method in structural tests can be based on scan design. In the scan design, internal registers can be configured into shift registers for test data delivery. The shift register is called a scan chain. There can be multiple scan chains. The scan chains can allow initialization of the internal registers for a given test prior to the test (controllability) and observation of the test response captured in the internal registers after the test for test decision (observability). Example of the scan-based design is shown in FIG. 1A. The scan enable (SE) can configure the internal registers into the scan chains. The SE can toggle between the scan shift mode for a test data delivery and the functional for a test response capture.
Most commonly applied structural tests are static and dynamic tests. Static tests can target detection of permanent defects that change circuit topology of the DUT. Similarly, dynamic tests can aim to detect delay defects that prevent devices from reaching their performance specifications. Examples of static and dynamic tests can be stuck-at test and at-speed transition test, respectively. The stuck-at test can target permanent defects by assuming their behavior as input or a output of logic gate in the DUT being stuck at logic one or zero. The transition test can target excessive delays caused by defects by modeling their behavior as slow transition in input or output port of a logic gate.
The scan-based design can increase test development efficiency by reducing a sequential depth during the ATPG. The sequential depth can be defined as a number of state transitions to reach a required state from a given initial state. The smaller the sequential depth, the more efficient ATPG from computational aspect. In case of the stuck-at test, for example, the scan-based DFT method can transform a sequential test problem into a combinational. The sequential depth of the combinational test can be zero.
Operation of the scan-based DFT method can be defined in a scan protocol. The scan protocol can be summarized as follows:                1. Load/unload scan chains        2. Force input        3. Measure output        4. Capture test responseIn the first step, the internal registers of the DUT can be configured into shift registers, if the SE=1. While the internal registers can be initialized by loading the test data into the shift register inputs, the shift register outputs can be measured for test decision. After completion of the scan load/unload, the internal registers can be configured back to the functional for testing, if the SE=0. The primary input of the DUT can be forced with the input stimulus to excite faults that model defects on the IO logic in the second step. In the third step, the primary output can be measured to observe faults on the IO logic. Finally, the test response of the DUT can be capture into the internal registers. The captured outputs can be observed while the scan chains are loaded. The The steps in the scan protocol can be repeated for each test pattern.        
The test pattern can be generated by the ATPG according to the scan protocol, as shown below. The scan input (SI) and the scan output (SO) denote the expected content of the internal registers before and after the capture, respectively. The SI can be shifted into the DUT and the output of the DUT can be compared against the SO for test decision during the scan load/unload. The primary input (PI) and the primary output (PO) denote the input stimulus applied to the primary input of the DUT and the expected output measured at the primary output, respectively. The input of DUT can be forced with the PI and the output can be compared with the PO for detection of faults.
Test Pat. No.Internal Reg (pre- & post-test)Primary Input & OutputTP #SISOPIPO
The DFT schemes and the ATPG methods can be coupled. The DFT architectural decision can affect capability and efficiency of the ATPG. Similarly, innovation in the ATPG technology can also influence the underlying DFT architectures.
The 3D IC system can comprise a set of interacting cores. The interacting cores can communicate via channels. Channel can have a source and a sink. Source can provide data to a channel and sink can consume the data from the channel. Communication can be achieved when the data provided by source is consumed by sink.
In digital circuits, a channel can be formed by a wire connecting output of one core (source) to input of other core (sink). The channel can be denoted with the name of the connecting wire. The same name of the output and the input can imply formation of a channel.
When communication is to be established, channel can create a communication constraint that requires input of sink to be the same as output of source. The communication constraint can be captured in a topology, e.g. an input-output dependency graph (IODG). Example of the IODG that represents the system comprising four interacting cores is shown in FIG. 1B. The IODG can consist of a set of vertices and edges. The vertices and the edges denote cores and channels, respectively. Source and sink are denoted with a tail and a head of an arrow in the IODG, respectively. The cores 0 through 3 can be interconnected to form a target system. The cores 0 and 3 can communicate to the system environment via the primary inputs and outputs. The primary IO can be a unidirectional or a bidirectional. All other cores are internal and do not directly communicate to the system environment. The system environment is explicitly shown in the IODG. The system environment can provide input to and receive output from the corresponding system. Thus, output and input of the system environment can be input and output of the system, respectively. The names of the PI and the PIO can be interpreted as the channels. Source and sink of the bidirectional channel can be determined by the output enable control.
Communication constraints can be imposed between the output of the source and the input of the sink. Satisfaction of the communication constrains can require information of both source and sink. Test development cost can depend on how information is presented in resolution of the communication constraints. In conventional ATPG approaches, design netlists of both source and sink are used to resolve their communication constraints. Communication constraints on pseudo-primary input and output can also be considered. The pseudo-primary input and output can be respectively output and input of internal storage cells or flip-flops (FFs) that comprise the scan chains. They, however, can be local or internal to each core, regardless of being source and sink, and can always be satisfied by the ATPG of each core.
For a core to be tested, the PI and the PO of the core are must be provided and measured, respectively. An environment that provides the PI to the core and measure the PO is defined as a test environment of the core. The test environment of an individual core can be generally provided by a set of cores and the system environment. Communication constraints can be considered as IO constraints to be satisfied between the core under test and the test environment with which the core interacts. Since the test environment can be unknown for the ATPG of an individual core performed independently, the communication constraints can also be unknown. Unavailability of communication constraints can prevent reuse of the core test patterns and can cause underutilization of test resources and inefficiency in both the ATPG and the system test.
Even if the test patterns are delivered to all cores, for example, only subset of the cores can be actually tested by the delivered test data. Inefficient use of test resources can be implied in the underutilized test data.
Without satisfying communication constraints, construction of the system-level test patterns from the independently generated core test patterns can be difficult, if not impossible. In other word, the ATPG is forced to be a generation-based and not a construction or composition-based.
Resolution of communication constraints can allow reuse of core test patterns, improve utilization and hence reduce both test cost and test development cost. It can also promote a modular approach in test logic insertion and the ATPG. The test logic insertion and the ATPG can be performed in each core independently without knowledge of its system environment. The test logic inserted cores can be composed through the common test integration platform that can allow uniform integration of independently implemented test logics. The ATPG of any levels of design hierarchy can be similarly performed to construct the test patterns from those of its lower level design constituents.
Scan Wrapper (IEEE STD 1500) can isolate each core under test from its system environment for the independent ATPG by inserting registers, called IO wrapper cells, in the channels connecting them. In the IEEE standard, the core under test can be tested in isolation without involvement of its system environment. The system environment of the core under test, called a parent, is blocked by a set of IO wrapper cells during the core test. Instead, the test environment of the core under test is forced through the IO wrapper cells. The inserted wrapper cells modify the channel behavior during the test. Each wrapper cell that block the channel for isolation can provide a test point during the test. The test point can be used to control input of the core or to observe the output. Underutilization of test resource, however, can be implied in the IEEE STD 1500. Mutually exclusive usage of the wrapper cells between core and its environment can imply that the core and the parent are not meant to be tested in the same test run. That is, the communication constraints for sequential execution of the core and the parent tests cannot be satisfied from their independently generated test patterns. It is also difficult to apply the core wrapper standard to dynamic test of the interface logic between the core and its parent.